(1) FIELD OF THE INVENTION
The present invention relates to ultra large scale integrated (ULSI) circuits on semiconductor substrates, and more particularly relates to a method for forming reliable stacked and borderless via structures for multilevel metal interconnections.
(2) DESCRIPTION OF THE PRIOR ART
The integrated circuits formed on semiconductor substrates for Ultra Large Scale Integration (ULSI) require multilevels of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. A dielectric layer, usually referred to as the Poly/Metal 1 Dielectric (PMD), is deposited over the field effect transistor (FET) polysilicon gate electrodes and substrate contacts to electrically insulate the devices from the next patterned metal layer. The different levels of metal interconnections are then separated by layers of insulating material, commonly referred to as Interlevel Metal Dielectric (IMD) layers. Both the PMD and IMD layers are commonly referred to as the InterLevel Dielectric (ILD) layers. These interposed dielectric (or insulating) layers have etched contact holes in the PMD layer to the underlying semiconductor devices or vias (holes) in the IMD layers which are used to electrically connect one level of metal to the next level of metal, and hereafter simply referred to as vias.
As the ULSI technology is scaled down to smaller dimensions, one of the most difficult obstacles to continued downscaling is controlling the level-to-level alignment of the photolithography. This is especially a problem in the complex structure of the interconnecting metal and vias as minimum device feature sizes reach 0.18 micrometers. Consequently, the packing density of the metal lines becomes limited by design ground rules governing the separation of the contact holes and/or vias from another level, that is by design rules that limit the nesting (stacking) of contact holes or vias in the ILD layer between the patterned conducting layers.
To better appreciate the advantages of using stacked and borderless contact holes and via structures, a sequence of schematic top views for the design layout of two levels of patterned metal and interconnecting vias is shown by the prior art in FIGS. 1A-1D for different design ground rules. In all FIGS. an insulating InterLayer Dielectric (ILD) 14 is deposited and contact holes or vias 4 are etched in the ILD 14 to the substrate 10, or to a patterned conducting layer (not shown) on the substrate. A patterned first metal layer 20 is formed on the ILD layer 14 over the vias 4, and a second ILD layer 14' is deposited to insulate the patterned metal layer 20. Vias 4' are etched in ILD 14' to metal layer 20 and a second metal layer 20' is patterned to form the second level of metal interconnections. The metal lines in FIG. 1A have borders (wider metal lines 20 and 20') to accommodate misalignment of the vias 4 and 4', and also the vias are not stacked (one over the other), and therefore require the larger design layout area. The metal lines in FIG. 1B do not require design rule separation between metal lines on different levels for via holes 4 and 4', and require less area. FIG. 1C shows stacked vias and metal-to-metal separation design rules, FIG. 1D shows borderless vias without via stacking, and FIG. 1E shows stacked and borderless via structures. It is clearly seen from FIG. 1E that the stacked and borderless via structures provide a space-saving advantage, which is about a 62% reduction in area. Therefore, it is very desirable to form stacked and borderless via structures that reduce the total area occupied by the metal inter-connections by about 62%. This results in an increased device packing density on the integrated circuit chip.
Unfortunately, several processing problems arise when stacked and borderless via structures are fabricated. These process problems are best illustrated by referring to the schematic cross-sectional views of a two-level metal having vias in the prior art FIGS. 2A-2D, FIGS. 3A-3C, and FIGS. 4 and 5.
FIGS. 2A-2D depict the problems with making stacked vias. In FIG. 2A no metal plug is used in the vias 4 and can result in poor electrical contacts causing current crowding and electromigration of metal atoms, while a good metal plug 3, as in FIG. 2B, ensures good via contacts. A poorly formed metal plug 3, as in FIG. 2C, can also result in poor via contacts. FIG. 2D shows a three-level metal structure with good metal plugs 3 and good via contacts, but unfortunately requires design rules for metal borders to prevent misalignment, as depicted in FIG. 3, when borderless vias are used. Making borderless via structures by the conventional method (by opening via, depositing metal, and patterning metal), as depicted in FIG. 4, can result in damage to the underlying metal 20 at location A when the upper metal 20' etch mask is misaligned over the via 4 in the ILD layer 14' during patterning of layer 20' and also reduces the contact area of metal 20' to metal 20 at location A in the via 4.
In the conventional Dual Damascene process, as shown in FIG. 5, a trench 2 is partially etched in the ILD layer 14' and the via 4 is etched to the underlying metal 20. The trench 2 and via 4 are filled with metal 20' and etched or polished back by chemical/mechanical polishing (CMP) to the surface of layer 14'. However, when the via 4 etching is misaligned to the trench 2, as would occur in borderless vias, then contact area B is very small resulting in high contact resistance. For example, in the 0.18 um technology, the metal line widths are about 0.2 um and a misalignment of 0.1 um would result only in a 0.1 um wide contact.
There is still a strong need in the semiconductor industry for providing a simplified method for forming self-aligned stacked and borderless via structures between the patterned metal levels which are not limited by the design rules.